1. Technical Field
The present invention relates to semiconductor fabrication, and more particularly to enabling enhanced reliability and mobility for replacement gate planar and FinFET structures.
2. Description of the Related Art
Incorporation of lanthanum oxide (La2O3) into high-k dielectric improves positive bias temperature instabilities (PBTI) and time-dependent dielectric breakdown (TDDB) on replacement gate fin field effect transistor (FinFET) and planar devices. However, there are multiple issues associated with this process. The electron mobility of n-type field effect transistor (nFET) devices is degraded potentially due to additional coulombic scatters, such as interface state generation and other traps from the formation of a La2O3/SiO2 interfacial dipole. The process of integrating the La2O3 into a functioning CMOS (complementary metal-oxide-semiconductor) flow results in negative bias temperature instabilities (NBTI) degrade due to excess nitrogen incorporation within the interfacial film. There are currently no known solutions to these problems.